Radyne DM240XR Spécifications télécharger pdf (Page 119)

DM240XR High-Speed Digital Modulator Remote Operations

MN-DM240XR– Revision 13 9–5

Source

<1>

Reserved

TBD, Default = 0

<11>

Reserved

TBD

<1>

Reserved

TBD

<1>

Major Alarm

Mask

Bit 0 = Spare

Bit 1 = Transmit Oversample PLL Lock

Bit 2 = FPGA Config Error

Bit 3 = IF Synthesizer PLL Lock

Bit 4 = External Reference PLL Lock

Bit 5 = Composite (SCT) PLL Lock

Bit 6 = Symbol PLL Lock

Bit 7 = Spare

0 = Mask, 1 = Allow

<1>

Minor Alarm

Mask

Bit 0 = Terrestrial Ethernet data activity detect

Bit 1 = Loss Terrestrial Clock

Bit 2 = Loss Terrestrial Data

Bit 3 = FIFO Error

Bit 4 = Output Level

Bit 5 = Terrestrial Framing Error

Bit 6 = Terr Ethernet jitter buffer underflow

Bit 7 = Terr Ethernet jitter buffer overflow

0 = Mask, 1 = Allow

<1>

Common Fault

Mask

Bit 0 = -12 V Alarm

Bit 1 = +12 V Alarm

Bit 2 = +5 V Alarm

Bit 3 = Spare

Bit 4 = Spare

Bit 5 = Spare

Bit 6 = Spare

Bit 7 = Spare

0 = Mask, 1 = Allow

<1>

Reserved

TBD, Default = 0

<4>

Symbol Rate

Symbol Rate in Symbols Per Second

<1>

Terrestrial

Framing

0 = 188 Byte, 1 = 204 Byte, 2 = No Framing

5 = COP3, 6 = ACM, 7 = Bridge

<1>

Roll Off

0 = 0.35, 25 = 0.25, 1 = 0.20

<1>

Reserved

TBD

<1>

Output Clock

Source

CTE, 1 = SCT, 2 = None

<1>

Network Spec

0 = DVB-S

9 = DirecTV

11 = DVB-S2 CCM

13 = Only DirecTV

15 = DVB-S2 ACM

1 2 ... 114 115 116 117 118 119 120 121 122 123 124 ... 195 196

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Radyne DM240XR Spécifications Page 119

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